1. Field of the Invention
Embodiments of the present invention relate generally to the field of accessing non-volatile memory. More particularly, embodiments of the present invention relate to accessing non-volatile memory with double data rate (DDR).
2. Description of the Related Art
Electronic devices may require high speed access to non-volatile memory contained within these devices. A prior global approach for DDR non-volatile memory access in an electronic device requires dividing the memory into memory blocks. Each of the memory blocks sends data signals to a global data synchronization register (DSR), which provides an interface between a 32-bit internal data bus and 8-bit I/O pads. Prior to data output, all 8-bytes from the memory via the internal data bus are preloaded to the global DSR which synchronizes the data signals with a clocking signal for the first data access. Data is globally sent from the global DSR to a global output buffer and then various I/O pads.
This global approach suffers from global parasitic interconnect delays between the memory blocks, global DSR, and global output buffer. Accessing various memory blocks may be more complicated and slower than accessing a single memory block.
It will be appreciated that for simplicity and clarity of illustration, elements illustrated in the figures have not necessarily been drawn to scale. For example, the dimensions of some of the elements may be exaggerated relative to other elements for clarity. Further, where considered appropriate, reference numerals have been repeated among the figures to indicate corresponding or analogous elements.